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Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators ADCMP604/ADCMP605
FEATURES
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB -40C to +125C operation
FUNCTIONAL BLOCK DIAGRAM
VCCI VCCO (ADCMP605 ONLY)
VP NONINVERTING INPUT
Q OUTPUT
ADCMP604/ ADCMP605
VN INVERTING INPUT
LVDS Q OUTPUT
LE/HYS INPUT
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)
SDN INPUT
(ADCMP605 ONLY)
Figure 1.
GENERAL DESCRIPTION
The ADCMP604/ADCMP605 are very fast comparators fabricated on the Analog Devices, Inc. proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCCI + 0.2 V, low noise, LVDS-compatible output drivers, and TTL/CMOS latch inputs with adjustable hysteresis and/or shutdown inputs. The devices offer 1.5 ns propagation delays with 1 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. A flexible power supply scheme allows the devices to operate with a single 2.5 V positive supply and a -0.5 V to +2.7 V input signal range up to a 5.5 V positive supply with a -0.5 V to +5.7 V input signal range. Split input/output supplies, with no sequencing restrictions on the ADCMP605, support a wide input signal range with greatly reduced power consumption. The LVDS-compatible output stage is designed to drive any standard LVDS input. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The ADCMP604 is available in a 6-lead SC70 package, and the ADCMP605 is available in a 12-lead LFCSP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2007 Analog Devices, Inc. All rights reserved.
05916-001
ADCMP604/ADCMP605 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Timing Information ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Application Information................................................................ 10 Power/Ground Layout and Bypassing..................................... 10 LVDS-Compatible Output Stage .............................................. 10 Using/Disabling the Latch Feature........................................... 10 Optimizing Performance........................................................... 10 Comparator Propagation Delay Dispersion ........................... 11 Comparator Hysteresis .............................................................. 11 Crossover Bias Points................................................................. 12 Minimum Input Slew Rate Requirement ................................ 12 Typical Application Circuits ......................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07--Rev. 0 to Rev. A Changes to Features and General Description ............................. 1 Changes to Electrical Characteristics Section .............................. 3 Changes to Table 3............................................................................ 6 Changes to Layout ............................................................................ 7 Changes to Figure 8.......................................................................... 8 Changes to Figure 14........................................................................ 9 Changes to Power/Ground Layout and Bypassing Section, and Using/Disabling the Latch Feature Section................................. 10 Changes to Comparator Hysteresis Section................................ 11 Changes to Crossover Bias Points Section .................................. 12 Changes to Ordering Guide .......................................................... 14 10/06--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP604/ADCMP605 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = -40C to +125C, typical at TA = 25 C, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Symbol VP, VN Conditions VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V Min -0.5 -0.2 -5.0 -5.0 -2.0 -0.1 V to VCCI -0.5 V to VCCI + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to +2.7 V VCCI = 2.5 V, VCCO = 5.0 V RHYS = Hysteresis is shut off Latch mode guaranteed VIH = VCCO + 0.2 V VIL = 0.4 V Current sink -1 A Hysteresis = 120 mV Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV Comparator is operating Shutdown guaranteed VIH = VCCO VIL = 0 V 10% output swing VOD = 50 mV, output valid VCCI = VCCO = 2.5 V to 5.0 V (ADCMP604) VCCO = 2.5 V to 5.0 V (ADCMP605) RLOAD = 100 RLOAD = 100 RLOAD = 100 RLOAD = 100 200 100 50 50 <0.1 2.0 -0.2 -6 -0.1 1.145 30 -25 VCCO +0.8 +6 +0.1 1.40 110 -8 Typ Max VCCI + 0.2 VCCI + 0.2 VCCI +5.0 +5.0 +2.0 7500 4000 Unit V V V mV A A pF k k dB dB dB mV V V A mA V k A ns ns ns ns V V A mA ns ns
VOS IP, IN CP, CN
2 1 750 370 62
Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP605 ONLY) VIH VIL IIH IIL HYSTERESIS MODE AND TIMING (ADCMP605 ONLY) Hysteresis Mode Bias Voltage Minimum Resistor Value Hysteresis Current Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP605 ONLY) VIH VIL IIH IIL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Differential Output Voltage Level VOD Common-Mode Voltage Peak-to-Peak Common-Mode Output
+0.4
1.25
tS tH tPLOH, tPLOL tPL
-2 2.7 20 24 2.0 -0.2 -6 VCCO +0.6 +6 -0.1
+0.4
tSD tH
1.4 25
VOD VOCI VOC (p-p)
245 1.125
350
445 50 1.375 50
mV mV V mV
Rev. A | Page 3 of 16
ADCMP604/ADCMP605
Parameter AC PERFORMANCE 1 Rise Time/Fall Time Propagation Delay Symbol tR, tF tPD Conditions 10% to 90% VCCI = VCCO = 2.5 V to 5.0 V, VOD = 50 mV VCCI = VCCO = 2.5 V, VOD = 10 mV VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V 10 mV < VOD < 125 mV VCM = -0.2 V to VCCI + 0.2 V VCCI = VCCO = 2.5 V to 5.0 V, PWOUT = 90% of PWIN 2.5 2.5 -3 -5.0 15 1.6 15 37 95 -50 0.92 -30 1.1 +30 Min Typ 600 1.6 3.0 70 70 1.6 250 500 1.3 Max Unit ps ns ns ps ps ns ps MHz ns
Propagation Delay Skew--Rising to Falling Transition Propagation Delay Skew--Q to QB Overdrive Dispersion Common-Mode Dispersion Input Bandwidth Minimum Pulse Width POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP605) Positive Supply Current (ADCMP604) Input Section Supply Current (ADCMP605) Output Section Supply Current (ADCMP605) Power Dissipation Power Supply Rejection Ratio Shutdown Mode ICCI Shutdown Mode ICCO
1
tPINSKEW
PWMIN
VCCI VCCO VCCI - VCCO VCCI - VCCO IVCCI/VCCO IVCCI IVCCO PD PSRR
Operating Nonoperating VCCI = VCCO = 2.5 V to 5.0 V VCCI = 2.5 V to 5.5 V VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V VCCI = VCCO = 5.0 V VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V
5.5 5.0 +3 +5.0 21 3.0 23 55 120
V V V V mA mA mA mW mW dB mA A
VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, VCCI = VCCO = 2.5 V, unless otherwise noted.
Rev. A | Page 4 of 16
ADCMP604/ADCMP605 TIMING INFORMATION
Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V LATCH ENABLE
tS tH
tPL
DIFFERENTIAL INPUT VOLTAGE
VIN VOD
VN VOS
tPDL
Q OUTPUT
tPLOH
50%
tPDH
tF
50%
tPLOL tR
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input-to-Output High Delay Input-to-Output Low Delay Latch Enable-to-Output High Delay Latch Enable-to-Output Low Delay Minimum Hold Time Minimum Latch Enable Pulse Width Minimum Setup Time Output Rise Time Output Fall Time Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages, VA and VB.
B
Rev. A | Page 5 of 16
05916-025
Q OUTPUT
ADCMP604/ADCMP605 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (SDN to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature Range, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V -0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA -40C to +125C 150C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type 6-Lead SC70 (KS-6) 12-Lead LFCSP_VQ (CP-12-1)
1
JA1 426 62
Unit C/W C/W
Measurement in still air.
ESD CAUTION
Rev. A | Page 6 of 16
ADCMP604/ADCMP605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Q1
6
Q VCCI /VCCO VN
05916-002
ADCMP604
VEE 2 VP 3 TOP VIEW (Not to Scale)
5 4
Figure 3. ADCMP604 Pin Configuration
Table 5. ADCMP604 Pin Function Descriptions (6-Lead SC70)
Pin No. 1 2 3 4 5 6 Mnemonic Q VEE VP VN VCCI/VCCO Q Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. VCCI and VCCO are shared pin. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN.
11 VEE
12 Q
VCCO 1
PIN 1 INDICATOR
10 Q
9 VEE 8 LE/HYS 7 SDN
VCCI 2 VEE 3
ADCMP605
TOP VIEW (Not to Scale)
Figure 4. ADCMP605 Pin Configuration
Table 6. ADCMP605 Pin Function Descriptions (12-Lead LFCSP_VQ)
Pin No. 1 2 3, 5, 9, 11 4 6 7 8 10 12 Heat Sink Paddle Mnemonic VCCO VCCI VEE VP VN SDN LE/HYS Q Q VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltages. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. Inverting Output. Q is at Logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Noninverting Output. Q is at Logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Rev. A | Page 7 of 16
05916-003
VEE 5
VN 6
VP 4
ADCMP604/ADCMP605 TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted.
800 600 400 VCC = 2.5V
CURRENT (A)
1.60 1.50 1.40
OUTPUT (V)
OUTPUT HI
VCC = 5.5V
200 0 -200 -400 -600
05916-010
1.30 1.20 1.10 1.00 0.90 2.4
OUTPUT VCM
OUTPUT LO
0
1
2 3 4 LE/HYS PIN (V)
5
6
7
2.9
3.4
3.9 4.4 VCCO (V)
4.9
5.4
5.9
Figure 5. LE/HYS Pin Current vs. Voltage
850
Figure 8. LVDS Output Level vs. VCCO (V)
200
800
150 100
750
RISE/FALL (ps)
700 +125C 650 600 550 500 450 2.80 3.20 3.60 4.00 4.40 VCCO (V) 4.80 5.20 5.60 6.00
05916-007 05916-008
CURRENT (A)
VCC = 2.5V 50 0 -50 -100 -150
VCC = 5.5V
+25C -40C
-1
0
1
2
3 4 SDN PIN (V)
5
6
7
05916-006
400 2.40
Figure 9. LVDS Output Rise/Fall Time vs. VCCO (V) Figure 6. SDN Pin Current vs. Voltage
250 10 +125C 8
HYSTERESIS (mV)
200
6 4 2
IB (A)
+25C -40C 150
0 -2 -4 -6 -8 -0.5 0.0 0.5 1.0 1.5 2.0 VCM AT VCC = 2.5V 2.5 3.0 3.5
05916-009
100 VCC = 2.5V 50 VCC = 5.5V 0 50 100 150 200 250 300 350 400 HYSTERESIS RESISTOR (k) 450 500
-10 -1.0
Figure 10. Hysteresis vs. Hysteresis Resistor
Figure 7. Input Bias Current vs. Input Common-Mode Voltage
Rev. A | Page 8 of 16
05916-011
-800 -1
ADCMP604/ADCMP605
350 300 250 +125C
0.44 0.43 0.42
HYSTERESIS (mV)
+25C 200 150 100 50 0 -40C
OUTPUT SWING (V)
05916-012
0.41 0.40 0.39 0.38 0.37
05916-013
05916-015
0
-2
-4
-6 -8 -10 -12 HYS PIN CURRENT (A)
-14
-16
-18
0.36 2.4
3.4
4.4 VCCO (V)
5.4
Figure 11. Hysteresis vs. HYS Pin Current
3.5
Figure 14. LVDS Output Swing vs. VCCO (V)
1.425V Q
PROPAGATION DELAY (ns)
3.0
2.5
2.0 PROPAGATION DELAY 1.5
Q 925.0mV
0 10 20 30 40 50 60 OVERDRIVE (mV) 70 80 90 100
05916-004
1.0
1.000ns/DIV
Figure 15. 50 MHz Output Voltage Waveform at VCCO = 2.5 V
Figure 12. Propagation Delay vs. Input Overdrive
1.6
1.543V
Q
PROPAGATION DELAY RISE ns 1.5
DELAY (ns)
PROPAGATION DELAY FALL ns 1.4
Q
05916-005
1.3 -0.6
1.043V
-0.2 0.2 0.6 1.0 1.4 1.8 VCM AT VCC (2.5V) 2.2 2.6 3.0
1.000ns/DIV
Figure 16. 50 MHz Output Voltage Waveform at VCCO = 5.5 V
Figure 13. Propagation Delay vs. Input Common-Mode Voltage
Rev. A | Page 9 of 16
05916-014
ADCMP604/ADCMP605 APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP604/ADCMP605 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. The use of low impedance supply planes is of critical importance particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCCI pin and the VCCO pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the package allows, and the input and output supplies have been connected separately (VCCI VCCO), be sure to bypass each of these supplies separately to the GND plane. Do not connect a bypass capacitor between these supplies. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation (VCCI = VCCO), coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs.
LVDS-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance is only achieved by keeping parasitic capacitive loads at or below the specified minimums. The outputs of the ADCMP604 and ADCMP605 are designed to directly drive any standard LVDScompatible input.
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can safely be left floating or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 70 k. This allows the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin disables all hysteresis. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected in parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V, regardless of VCCO.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals. Higher impedances encourage undesired coupling.
Rev. A | Page 10 of 16
ADCMP604/ADCMP605
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP604/ADCMP605 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal is driven past the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communications, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (see Figure 17 and Figure 18). The ADCMP604/ADCMP605 dispersion is typically <1.6 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because each of the ADCMP604 and ADCMP605 has substantially equal delays for positive-going and negative-going inputs and very low output skews.
500mV OVERDRIVE
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 19. As the input voltage approaches the threshold (0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2.
OUTPUT
VOH
VOL
INPUT VOLTAGE 10mV OVERDRIVE VN VOS
-VH 2
0V
+VH 2
INPUT
Figure 19. Comparator Hysteresis Transfer Function
Q/Q OUTPUT
Figure 17. Propagation Delay--Overdrive Dispersion
INPUT VOLTAGE 1V/ns VN VOS 10V/ns
05916-016
DISPERSION
The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. The ADCMP605 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND varies the amount of hysteresis in a predictable and stable manner. Leaving the LE/HYS pin disconnected or driving it high removes hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 20 illustrates the amount of hysteresis applied as a function of external resistor value. Figure 11 illustrates hysteresis as a function of current.
Q/Q OUTPUT
Figure 18. Propagation Delay--Slew Rate Dispersion
05916-017
DISPERSION
Rev. A | Page 11 of 16
05916-018
ADCMP604/ADCMP605
The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 70 k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it would likely degrade the jitter performance of the device and impair the latch function. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function.
250
CROSSOVER BIAS POINTS
Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCCI rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCCI/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PCB. In many applications, chattering is not harmful.
200
HYSTERESIS (mV)
150
100 VCC = 2.5V 50 VCC = 5.5V 50 100 150 200 250 300 350 400 HYSTERESIS RESISTOR (k) 450 500
05916-026
0
Figure 20. Hysteresis vs. RHYS Control Resistor
Rev. A | Page 12 of 16
ADCMP604/ADCMP605 TYPICAL APPLICATION CIRCUITS
2.5V TO 5V 0.1F INPUT 2k
2.5V
2k
ADCMP604
CMOS OUTPUT
05916-019
0.1F
ADCMP604
INPUT 1.25V 50mV
LVDS PWM OUTPUT
Figure 21. Self-Biased, 50% Slicer
2.5V TO 3.3V
INPUT 1.25V REF 10k 10k
ADCMP601
LVDS 100
ADCMP604
LVDS
05916-020
10k
82pF
LE/HYS
05916-023
05916-024
100k
Figure 22. LVDS to Repeater
2.5V TO 5V
Figure 25. Oscillator and Pulse-Width Modulator
2.5V TO 5V
ADCMP605
ADCMP605
DIGITAL INPUT
74VHC 1G07
LE/HYS 150k
DIGITAL INPUT
74AHC 1G07
LE/HYS
CONTROL VOLTAGE 0V TO 2.5V
05916-021
150k
HYSTERESIS CURRENT
10k
Figure 23. Hysteresis Adjustment with Latch
2.5V
Figure 26. Hysteresis Adjustment with Latch
10k
82pF
ADCMP605
LE/HYS
LVDS OUTPUT
150k
150k
Figure 24. Voltage-Controlled Oscillator
05916-022
CONTROL VOLTAGE 0V TO 2.5V
10k
Rev. A | Page 13 of 16
ADCMP604/ADCMP605 OUTLINE DIMENSIONS
2.20 2.00 1.80 2.40 2.10 1.80
1.35 1.25 1.15 PIN 1 1.30 BSC 1.00 0.90 0.70
6 1
5 2
4 3
0.65 BSC 1.10 0.80 0.40 0.10 0.46 0.36 0.26
0.10 MAX
0.30 0.15 0.10 COPLANARITY
SEATING PLANE
0.22 0.08
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-6) Dimensions shown in millimeters
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 0.50 BSC 0.75 0.55 0.35
0.60 MAX
PIN 1 INDICATOR *1.45 1.30 SQ 1.15
9 8 7
10
11 12
1 2
6
5
4
3
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADCMP604BKSZ-R2 1 ADCMP604BKSZ-REEL71 ADCMP604BKSZ-RL1 ADCMP605BCPZ-WP1 ADCMP605BCPZ-R21 ADCMP605BCPZ-R71 EVAL-ADCMP605BCPZ1
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
Package Option KS-6 KS-6 KS-6 CP-12-1 CP-12-1 CP-12-1
Branding G0Q G0Q G0Q G0K G0K G0K
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
ADCMP604/ADCMP605 NOTES
Rev. A | Page 15 of 16
ADCMP604/ADCMP605 NOTES
(c)2006-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05916-0-8/07(A)
T T
Rev. A | Page 16 of 16

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